EE 312 Digital Electronics

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2009/2010 Spring Term

 

 

Sec

Instructor

Office

E-mail Address

WEB Address

1

Murat Aşkar

D-211

askarm@metu.edu.tr

http://www.eee.metu.edu.tr/~askar/

2

Tayfun Akın

D-108

tayfun-akin@metu.edu.tr

http://www.eee.metu.edu.tr/~tayfuna/

3

Barış Bayram

C-105

bbayram@metu.edu.tr

http://www.eee.metu.edu.tr/~bbayram/

4

Haluk Külah

DZ-05

kulah@metu.edu.tr

http://www.eee.metu.edu.tr/~kulah/

 

 

Documents for 2008/2009 Spring Semester

 

1. Syllabus

 

Chapter

                                  TOPIC

Hours

SS, LN

Overview of Digital Circuit Design (10.1)

2 hr

DC+WEB

Diodes (2.1-4s), Diode Resistor Logic (2.5) TH

RA

SS

Bipolar Junction Transistors, The Ebers-Moll Model (5.1-5.2) TH

2 hr

SS

Resistor-Transistor Logic (RTL) (5.3.1, 5.3.4)

1 hr

SS

BJT Circuits DC Analysis (5.4) TH

1 hr

DC

Diode-Transistor Logic (DTL) Spice TH

1 hr

DC

Transistor-Transistor Logic (TTL) (Examples 7.3&7.4) (7.9, 7.10 R.A.) Spice TH

3 hr

DC

Schottky Transistor and STTL (8)

1 hr

SS

MOS Field Effect Transistors (4.1 RA, 4.2.1, 4.2.2,4.2.4, 4.2.5, 4.2.8 RA, 4.3 RA 4.4, 4.11)

2 hr

SS

Pseudo NMOS Logic (10.4)

2 hr

SS+LN

CMOS Inverter (4.10, 10.2), Tri-State Buffer

2 hrs

SS

CMOS Combinational Logic Gates (10.3) TH

1 hr

DC

Comparison and Interfacing of Logic Families

2 hr

SS

Pass Transistor Logic (10.5)

1 hr

SS

Dynamic Logic Circuits and Domino CMOS Logic (10.6)

1 hr

LN Interfacing Logic Gates

2 hr

SS

Regenerative Circuits, Schmitt-Trigger (13.4) TH

2 hr

SS

Latches and Flip Flops (11.1) Schmitt-Trigger (13.4)

1 hr

SS

Multivibrator Circuits (Monostable, Astable, Ring Oscillator) (11.2, 13.5)

2 hr

SS

The 555 Integrated Circuit Timer (13.7) TH

3 hr

SS

Random Access Memories (RAM), Read-Only Memories (ROM) (11.3, 11.4, 11.5, 11.6)

4 hr

SS

Data Converters, Digital-to-Analog (D/A) and (9.7, 9.8) TH

3 hr

SS

Analog-to-Digital (A/D) Converters, (9.9) TH

3 hr

 

Total

40 hr

  Midterm 1 topics  
  Midterm 2 topics  

 

 

Take Home Exams (2009/2010)

No

Homework

Sol'n

Due

Teaching Asistant e-mail Tel Room

1

Transistor State Finding

Sol

16/17 March 2010

Koray Ozdal OZKAN koray@eee.metu.edu.tr 4412 DZ-10

2

RTL and DTL Gates

Sol

23/24 March 2010

Koray Ozdal OZKAN koray@eee.metu.edu.tr 4412 DZ-10
3 DTL and TTL Gates Sol 30/31 March 2010 İlker EROL   erol_ilker@yahoo.com 4587 E-102
4 TTL Gates Sol 13/14 April 2010 Yasemin ÖZKAN AYDIN yasemino@eee.metu.edu.tr 4426/ 4558 A-405/ A-308
5 NMOS Inverter Sol 21/22 April 2010 Reyhan ZENGİN

reyhan@eee.metu.edu.tr 

4407 DZ-02
6 CMOS Inverter Sol 28/28 April 2010 İlker EROL   erol_ilker@yahoo.com 4587 E-102
7 555 Timer Sol 11/12 May 2010 Yasemin ÖZKAN AYDIN yasemino@eee.metu.edu.tr 4426/ 4558 A-405/ A-308
8 Interfacing and Regenerative Circuits Sol 17/18 May 2010 Reyhan ZENGİN

reyhan@eee.metu.edu.tr

4407 DZ-02
9 Data Converters   26/27 May 2010 İlker EROL   erol_ilker@yahoo.com 4587 E-102
10 Memory   7 June 2010 Yasemin ÖZKAN AYDIN yasemino@eee.metu.edu.tr 4426/ 4558 A-405/ A-308